ISL97671IRZ-EVALZ【PDF 15/27 页】BOARD EVALUATION FOR ISL97671

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ISL97671

25%. Hitting of the upper threshold will also set the thermal fault

bit of the Fault/Status register 0x02. Unless disabled via the EN

pin, the device stays in an active state throughout, allows the

external processor to interrogate the fault condition.

For the extensive fault protection conditions, please refer to

Figure 25 and Table 1 for details.

V IN

LX

V OUT

DRIVER

IMAX

ILIMIT

FAULT

LOGIC

O/P

SHORT

FET

DRIVER

LX

OVP

VSET/2

VSC

CH0

CH5

REG

THRM

SHDN

OTP

REF

T2

TEMP

SENSOR

T1

VSET

+

Q0 VSET

+

Q5

-

PWM/OC0/SC0

-

PWM/OC5/SC5

FAULT/

STATUS

SMBUS/I 2 C

CONTROL

REGISTER

LOGIC

DC CURRENT

FIGURE 25. SIMPLIFIED FAULT PROTECTIONS

TABLE 1. PROTECTIONS TABLE

CASE

1

FAILURE MODE

CH0 Short Circuit

DETECTION MODE

Upper Over-Temperature

FAILED CHANNEL ACTION

CH0 ON and burns power.

GOOD CHANNELS ACTION

CH1 through CH5 Normal

V OUT REGULATED

BY

Highest VF of

Protection limit (OTP) not

triggered and CH0 < 4V

CH1 through CH5

2

CH0 Short Circuit

Upper OTP triggered but

All channels go off until chip cooled

Same as CH0

Highest VF of

VCH0 < 4V

and then comes back on with

current reduced to 76%. Subsequent

OTP triggers will reduce I OUT further.

CH1 through CH5

3

CH0 Short Circuit

Upper OTP not triggered

CH1 disabled after 6 PWM cycle

CH1 through CH5 Normal

Highest VF of

but CH0 > 4V

time-out.

CH1 through CH5

4

CH0 Open Circuit

with infinite

Upper OTP not triggered

and CH0 < 4V

V OUT will ramp to OVP. CH1 will time- CH1 through CH5 Normal

out after 6 PWM cycles and switch

Highest VF of

CH1 through CH5

resistance

off. V OUT will drop to normal level.

5

CH0 LED Open Circuit Upper OTP not triggered

CH1 remains ON and has highest VF, CH1 through CH5 ON, Q1 through VF of CH0

but has paralleled

Zener

and CH0 < 4V

15

thus V OUT increases.

Q5 burn power

FN7631.3

August 14, 2012

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